Memory system and memory card

ABSTRACT

A memory system includes a plurality of nonvolatile memory chips (CHP 1  and CHP 2 ) each having a plurality of memory banks (BNK 1  and BNK 2 ) which can perform a memory operation independent of each other and a memory controller ( 5 ) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

TECHNICAL FIELD

The present invention relates to a memory system and a memory card eachusing a plurality of chips of nonvolatile memories such as flashmemories having multiple banks and relates to a technique effective whenapplied to a memory card such as a multimedia card.

BACKGROUND ART

A flash memory can store information in accordance with a thresholdvoltage changed by injecting or discharging electrons to/from a floatinggate or the like of a memory cell transistor. In the specification, astate where the threshold voltage of the memory cell transistor is lowwill be called an erase state, and a state where the threshold voltageis high will be called a write state. In the case of storing informationin accordance with write data, a high voltage is applied to a memorycell transistor in the erase state in accordance with a logic value ofthe write data. To obtain a desired threshold voltage in the memory celltransistor, relatively long processing time is required.

There is a conventional flash memory card on which a flash memory chipand a memory controller are mounted and which employs an interleavewriting operation to achieve seemingly high speed of the writingoperation. The interleave writing operation is performed in such amanner that a plurality of flash memory chips are mounted on a cardboard, one of the flash memory chips is instructed to perform a writingoperation and, after that, another flash memory is instructed to performa writing operation and starts the writing operation. To make writingoperation time unseen by the operation, a number of flash memory chipshave to be mounted. Specifically, when write setup time for supplying awrite address and write data to one flash memory chip and giving aninstruction to perform the writing operation is compared with time ofthe writing operation of writing the write data into the memory addressinstructed by the write setup, the writing operation time is muchlonger. If the write setup is sequentially made to the other flashmemories so as to overlap the writing operation time, the writingoperations on most of the flash memory chips can be performed partiallyin parallel, so that the writing operation time of many of the flashmemory chips is unseen.

However, in the conventional method of performing interleave writing onthe flash memory unit basis, a number of flash memory chips have to bemounted to make the writing operation time unseen, so that the size andcost of the memory card increases.

An object of the invention is to provide a memory system and, further, amemory card capable of realizing higher write speed without mountingflash memory chips of the number which is large to an extent that thesize of the memory card increases or the cost increases.

The above and other objects and novel features of the invention willbecome apparent from the description of the specification and theappended drawings.

DISCLOSURE OF THE INVENTION

[1] A memory system according to the invention includes a plurality ofnonvolatile memory chips each having a plurality of memory banks whichcan perform a memory operation independent of each other, and a memorycontroller which can control to individually access each of thenonvolatile memory chips. The memory controller can selectively instructa simultaneous writing operation or an interleave writing operation onthe plurality of memory banks in the nonvolatile memory chips.

According to the means, the simultaneous writing operation or interleavewriting operation on a plurality of memory banks can be performed inunits of a chip having multiple banks. In the simultaneous writingoperation, the writing operation which is much longer than the writesetup time can be performed perfectly in parallel. In the interleavewriting operation, the writing operation following the write setup onone memory bank is sequentially performed and partially overlaps thewriting operation on another memory bank, thereby performing theoperations in parallel. Thus, the number of nonvolatile memory chipsconstructing the memory system performing the high-speed writingoperation can be made relatively small.

The simultaneous writing operation is, for example, a writing operationstarted at the same timing on a plurality of memory banks after serialplural instructions of the writing operation designating the memorybanks. The interleave writing operation is a writing operation ofstarting a new writing operation in response to a write instructiondesignating another memory bank during a writing operation which hasalready started.

As a desired mode of the invention, the memory controller maydiscriminate between an instruction of the simultaneous writingoperation and an instruction of the interleave writing operation inaccordance with a kind of a command code which accompanies write addressinformation and write data information and instructs a writingoperation. Although the writing operation can be also instructed byregister setting, as compared with this case, a special control mode canbe omitted. It is sufficient to give a write command so as to accompanythe write address information and write data information.

As a preferred mode of the invention, when each of the nonvolatilememory chips has a chip select terminal and other plural accessterminals, to easily obtain a connection mode in which the memorycontroller can access each of the plurality of nonvolatile memory chips,the memory controller has a chip select signal output terminal connectedto the chip select terminal of each of the nonvolatile memory chips anda plurality of access information terminals commonly connected to theaccess terminals of each of the nonvolatile memory chips.

[2] A memory system according to another aspect of the inventionincludes a plurality of nonvolatile memory chips each having a pluralityof memory banks which can perform a memory operation independent of eachother, and a memory controller which can control to individually accesseach of the nonvolatile memory chips. The memory controller cansequentially instruct interleave writing on the memory banks in each ofthe nonvolatile memory chips.

The interleave writing instruction is, for example, a writing operationinstruction for starting a new writing operation in response to a writeinstruction designating another memory bank during a writing operationalready started.

According to the means, the interleave writing operation on a pluralityof memory banks can be performed in units of a chip having multiplebanks. In the interleave writing operation, the writing operationfollowing the write setup on one memory bank is sequentially performedand partially overlaps the writing operation on another memory bank,thereby performing the operations in parallel. Thus, the number ofnonvolatile memory chips constructing the memory system performing thehigh-speed writing operation can be made relatively small.

[3] A memory system according to another aspect of the inventionincludes a plurality of nonvolatile memory chips each having a pluralityof memory banks which can perform a memory operation independent of eachother, and a memory controller which can control to individually accesseach of the nonvolatile memory chips. The memory controller cansequentially instruct simultaneous writing on the memory banks in eachof the nonvolatile memory chips.

The simultaneous writing instruction is, for example, a writingoperation instruction for starting the writing operation at the sametiming on a plurality of memory banks after serial plural instructionsof the writing operation designating the memory banks.

According to the means, the simultaneous writing operation on aplurality of memory banks can be performed in units of a chip havingmultiple banks. In the simultaneous writing operation, the writingoperation much longer than the write setup time can be performedperfectly in parallel. Thus, the number of nonvolatile memory chipsconstructing the memory system performing the high-speed writingoperation can be made relatively small.

[4] A memory system according to further another aspect of the inventionincludes a plurality of flash memory chips each having a plurality ofmemory banks which can perform a memory operation independent of eachother, a memory controller which can control to individually access eachof the plurality of flash memory chips, and an SRAM connected to thememory controller. The SRAM can temporarily store write data to theflash memory chips. The memory controller can select an instruction ofsequentially performing interleave writing on the memory banks in eachof the flash memory chips or an instruction of sequentially performingsimultaneous writing the memory banks in each of the flash memory chips.

In the case where the transfer speed of write data sent from a hostsystem is faster than the speed of operation of writing data to theflash memory chip by the interleave writing or simultaneous writing, theSRAM is used as a write data buffer. In the case where the write speedis faster than the data transfer speed, it is unnecessary to use theSRAM as a write data buffer.

[5] A memory system according to further another aspect of the inventionincludes a plurality of flash memory chips each having a plurality ofmemory banks which can perform a memory operation independent of eachother and a memory controller which can control to access the flashmemory chip by using an access command. The memory controller outputs afirst command code, address information of a memory bank subsequent tothe first command code, and a second command code subsequent to theaddress information of the memory bank and makes a memory bankdesignated by the address information start a memory operation everyinput of the second command code. The memory controller also outputs afirst command code, address information of a memory bank subsequent tothe first command code, a third command code subsequent to the addressinformation of the memory bank, address information of a memory banksubsequent to the third command code, and a second command codesubsequent to the address information of the memory bank, and makes aplurality of memory banks designated by a plurality of pieces of addressinformation separated by the third command between the first commandcode to the second command code simultaneously start a memory operationin response to input of the second command code. The former operation isthe interleave writing operation, and the latter operation is thesimultaneous writing operation.

The first command code is a command code indicative of a kind of thewriting operation, the second command code is a command code forinstructing start of the writing operation, and the third command codeis a command code indicating that address information follows.

[6] A memory card according to the invention has, on a card board, anexternal connection terminal, an external interface circuit connected tothe external connection terminal, a memory controller connected to theexternal interface circuit, and a plurality of flash memory chips eachreceiving an access control by the memory controller. The flash memorychip has a plurality of memory banks which can perform a memoryoperation independent of each other. The memory controller canselectively instruct a simultaneous writing operation or an interleavewriting operation on a plurality of memory banks in the flash memorychips.

As a write data buffer, an SRAM may be mounted. In the case of applyingthe invention to a multimedia card or the like, the external connectionterminal includes a 1-bit data input/output terminal, a 1-bit commandterminal, a power source voltage terminal, a circuit's ground voltageterminal, and a clock terminal.

Also in the memory card, in a manner similar to the above, in thesimultaneous writing operation, the writing operation much longer thanthe write setup time can be performed perfectly in parallel. In theinterleave writing operation, the writing operation following the writesetup of one memory bank can be performed sequentially so as topartially overlap the writing operation on another memory bank, therebyperforming the operations in parallel. As a result, the number ofnonvolatile memory chips required to construct a memory card of ahigh-speed writing process can be made relatively small, rise in cost ofthe memory card is suppressed, and the writing operation can beperformed at higher speed.

[7] A nonvolatile semiconductor memory device according to the inventionhas a memory controller and one or more nonvolatile memories. The memorycontroller issues a write instruction command including addressinformation indicative of an address in which information is to bewritten to the one or more nonvolatile memories. A first nonvolatilememory in the nonvolatile memories has a plurality of storage regionswhich are separated by addresses and can be accessed in parallel. Thememory controller issues a first write instruction command forinstructing writing of information into an address included in a firststorage region in the first nonvolatile memory and, before completion ofa writing operation in the first storage region, issues a second writeinstruction command for instructing writing of information to an addressincluded in a second storage region in the first nonvolatile memory.

The nonvolatile memory has, for example, a plurality of memory cells anda writing operation of the nonvolatile memory is performed by selectinga group of memory cells in accordance with an address instructed by thewrite instruction command and changing a threshold voltage according toinformation to be written into each of the selected memory cells.

The writing operation of the nonvolatile memory includes, for example, afirst operation for changing the threshold voltage of a memory cell, anda second operation for confirming whether the threshold voltage of eachof the memory cells has changed to a threshold voltage corresponding tothe information to be written. In the case where the threshold voltageof at least one memory cell has not changed to a threshold voltagecorresponding to information to be written after the second operation,the first operation is performed.

In the plurality of memory cells, for example, a threshold voltageincluded in a threshold voltage distribution corresponding toinformation to be written out of three or more threshold voltagedistributions is set.

[8] A nonvolatile memory device according to the invention has: a firstterminal used for inputting/outputting data; a second terminal used forinputting an operation instruction command; and a third terminal usedfor inputting/outputting data and for inputting a clock instructing atiming of inputting the operation instruction command. The nonvolatilememory device further includes: a control unit for controlling anoperation according to the operation instruction command input from thesecond terminal; and one or more nonvolatile memories to/from which datais stored/read on the basis of control of the control unit. Thenonvolatile memory has a plurality of memory cells corresponding toaddresses, the plurality of memory cells are divided into a plurality ofgroups and, during a data storing operation of a first group, a datastoring operation is started in another group.

For example, the control unit divides data input from the first terminalevery predetermined bytes, instructs to store first data into the firstgroup of a first nonvolatile memory, and instructs to store second datainto a second group of the first nonvolatile memory.

In the above, the control unit issues, for example, a storageinstruction command for instructing a storing operation to thenonvolatile memory. The storage instruction command is constructed by afirst command indicating that the command is a storage instructioncommand, address information for instructing a memory cell to which datais to be stored, data to be stored, and a second command for instructingstart of a storing operation.

In the above, the control unit issues, for example, the first command, afirst address designating a memory cell in the first group in the firstnonvolatile memory, the first data, the second command, after that, thefirst command, a second address designating a memory cell in the secondgroup in the first nonvolatile memory, the second data, and the secondcommand.

In the above, the control unit issues the first command, a first addressdesignating a memory cell in the first group in the first nonvolatilememory, the first data, after that, the first command, a second addressdesignating a memory cell in the second group in the first nonvolatilememory, the second data, and the second command.

From another viewpoint, for example, the control unit divides data inputfrom the first terminal every predetermined bytes, instructs to storefirst data into the first group of a first nonvolatile memory, andinstructs to store second data into the first group of a secondnonvolatile memory.

In the above, the control unit issues the first command, a first addressdesignating a memory cell in the first group in the first nonvolatilememory, the first data, the second command, after that, the firstcommand, a second address designating a memory cell in the first groupin the second nonvolatile memory, the second data, and the secondcommand.

In the above, for example, the control unit issues the first command, afirst address designating a memory cell in the first group in the firstnonvolatile memory, the first data and, after that, the first command, asecond address designating a memory cell in the first group in thesecond nonvolatile memory, the second data, and the second command.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a memory card as an example of amemory system according to the invention.

FIG. 2 is a timing chart illustrating a setup operation (write setupoperation) and a memory operation (writing operation) for writing.

FIG. 3 is a timing chart illustrating a 1-bank operation of operatingmemory banks one by one in a flash memory chip which is selected tooperate.

FIG. 4 is a timing chart illustrating simultaneous writing of two banks.

FIG. 5 is a timing chart illustrating an interleave writing operation.

FIG. 6 is a diagram illustrating writing operation timings and writespeed for each of writing operation modes.

FIG. 7 is a diagram showing the relation between the number of memorybanks and write speeds in each of interleave writing and simultaneouswriting when N=2 Kbytes, Tsetup=100 μsec, and Tprog=1000 μsec.

FIG. 8 is a diagram illustrating writing operation timings and writeoperation speeds when U pieces of 1-bank flash memory chips are used.

FIG. 9 is a diagram illustrating simultaneous writing operation timingsand white operation speeds when U pieces of S-bank flash memory chipsare used.

FIG. 10 is a diagram illustrating interleave writing operation timingsand writing operation speeds when U pieces of S-bank flash memory chipsare used.

FIG. 11 is a diagram illustrating the relation between the number ofchips and the number of memory banks at which the write speed becomesthe highest in each of the writing operation modes in FIGS. 8 to 10.

FIG. 12 is a block diagram of a multimedia card to which the inventionis applied.

FIG. 13 is a diagram illustrating the writing operation mode and theoperation timings when a form of one bank in one chip is used.

FIG. 14 is a diagram illustrating the writing operation mode and theoperation timings when a form of one bank in two chips is used.

FIG. 15 is a diagram illustrating the writing operation mode and theoperation timings when a form of simultaneously writing two banks in onechip is used.

FIG. 16 is a diagram illustrating the writing operation mode and theoperation timings when a form of simultaneously writing two banks ineach of two chips is used.

FIG. 17 is a diagram illustrating the writing operation mode and theoperation timings when a form of interleave writing two banks in onechip is used.

FIG. 18 is a diagram illustrating the writing operation mode and theoperation timings when a form of interleave writing two banks in each oftwo chips is used.

FIG. 19 is a block diagram generally showing an example of a flashmemory chip.

FIG. 20 is a block diagram showing an example of a memory bank.

FIG. 21 is a diagram illustrating a sectional structure of a nonvolatilememory cell.

FIG. 22 is a circuit diagram illustrating a part of an AND-type memorycell array.

FIG. 23 is a diagram illustrating states of applying erase and writevoltages to a memory cell.

FIG. 24 is a diagram illustrating commands of the flash memory.

BEST MODE FOR CARRYING OUT THE INVENTION

Memory System

FIG. 1 shows a memory card as an example of a memory system according tothe invention. A memory card 1 shown in the diagram has, on a card board2, plural nonvolatile memory chips, for example, two flash memory chipsCHP1 and CHP2 each having plural, for example, two memory banks BNK1 andBNK2 which can operate independently of each other, a memory controller5 which can control an access to each of the flash memory chips CHP1 andCHP2, and an SRAM 6 connected to the memory controller 5. The SRAM 6 canbe used as a data buffer for temporarily storing write data onto theflash memory chips CHP1 and CHP2. The memory controller 5 canselectively instruct the simultaneous writing operation or interleavewriting operation on the memory banks BNK1 and BNK2 of the flash memorychips CHP1 and CHP2.

The details of the flash memory chips CHP1 and CHP2 will be describedlater. The functions for responding to the instruction of thesimultaneous writing operation or the interleave writing operation willbe described first. Each of the flash memory chips CHP1 and CHP2 has achip select terminal /CE, a reset terminal /RES, a write enable terminal/WER, an output enable terminal /OE, a command data enable terminal/CDE, a serial clock terminal SC, an input/output terminal I/O[0:7], anda ready/busy terminal R/B. The input/output terminal I/O[0:7] iscommonly used for data input/output, address input, and command input.The command input from the input/output terminal I/0[0:7] issynchronized with a change in the command data enable signal /CDE. Thedata input/output is synchronized with a serial clock SC. Addressinformation is input synchronously with a change in the write enablesignal /WE.

Selection of an operation on the flash memory chip CHP1 is instructed bya chip select signal /CE0 from the memory controller 5, and selection ofan operation on the flash memory chip CHP2 is instructed by a chipselect signal /CE1 from the memory controller 5. Other interfaceterminals of the flash memory chips CHP1 and CHP2 are commonly connectedto corresponding terminals of the memory controller 5.

Memory operations on the flash chips CHP1 and CHP2 selected by the chipenable signals /CE0 and /CE1 are instructed by a command and addressinformation supplied via the input/output terminal I/O[0:7] and, asnecessary, write data. The address information includes designationinformation of the memory bank BNK1 or BNK2 and information of an accessaddress in the designated memory bank. An operation of instructing thememory operation will be called a setup operation. Since the setupoperation always needs an interface to the outside, it has to be doneserially every memory bank. According to the instruction given by thesetup operation, the flash chip CHP1 or CHP2 selected to operateperforms a memory operation of writing, erasing, or reading data to/froma flash memory cell. The memory operation can be performed independentlyfor each of the banks in accordance with access control informationsupplied in the setup operation. Therefore, the memory operation can beperformed in memory banks in parallel.

FIG. 2 is a timing chart showing the setup operation (write setupoperation) and a memory operation (writing operation) for writing. “10H”which is input in the write setup operation denotes a write command,“SA(1) and SA(2)” denote sector addresses, “CA(1) and CA(2)” indicatecolumn addresses, “Din1 to DinN” indicate write data, and “40H”expresses a write start command.

In FIG. 2, time of writing operation (writing operation time Tprog) ismuch longer than that of write setup (write setup time Tsetup). Anamount of the write data Din1 to DinN is generally large, and the writesetup time Tsetup is proportional to the amount of write data inputsynchronously with the serial clock SC.

FIG. 3 is a timing chart of a one-bank operation of making memory banksoperate one by one in a flash memory chip selected to operate. The writedata is expressed as Din1 to DinN. The writing operation is performed oneach of the memory banks BNK1 and BNK2 serially.

FIG. 4 is a timing chart showing two-bank simultaneous writing. It takesabout twice as long as the write setup time Tsetup to input a commandand the like but operation time of the two memory banks BNK1 and BNK2 isonly the time Tprog since the operations are performed in parallel.

FIG. 5 is a timing chart of the interleave writing operation. In thetwo-bank simultaneous writing operation, before starting the memoryoperation in response to an instruction of the writing operationdesignating one of the memory banks, if there is an instruction of thewriting operation designating another memory bank, the writing operationis performed on both of the memory banks in parallel. In contrast, theinterleave writing operation is performed in such a manner that evenduring the memory operation performed in response to an instruction ofthe writing operation designating one of the memory banks, the memoryoperation can be performed in response to an instruction of the writingoperation designating another memory bank. Time Tx denotes time fromissue of the command code “40H” instructing start of the writingoperation to issue of the sector address of the following writingoperation. The time can be set substantially equal to zero.

Command codes of the write access command in the write setup operationof FIG. 4 are “10H”, “41H”, and “40H”. Command codes of the write accesscommand in the write setup operation in FIG. 5 are “10H”, “40H”, and“40H”. If the time Tx in FIG. 5 is substantially zero, the write setupoperation time for two-bank parallel simultaneous writing in FIG. 4 andthe write setup operation time for the interleave writing operation ofFIG. 5 become substantially equal to each other. In short, the two-bankparallel simultaneous writing operation time of FIG. 4 and theinterleave writing operation time of FIG. 5 becomes 2Tsetup+Tprog at theshortest. In contrast, in the one-bank operation of FIG. 3, the shortesttime of writing on the two memory banks BNK1 and BNK2 is 2Tsetup+2Tprog.

As described above, the parallel simultaneous writing operation or theinterleave writing operation on the plural memory banks is selectivelyinstructed to the flash memory chips CHP1 and CHP2 in accordance with acommand code given in the setup operation. Since the parallel writing orinterleave writing operation can be performed on the plurality of memorybanks 3 and 4, the period of the busy state by the writing operation canbe shortened. In short, the process performed in response to theinstruction of the writing operation from the memory controller 5 can beperformed at higher speed.

It was understood from the above that the writing process can beperformed at higher speed by the parallel writing or interleave writingoperation in the flash memory chip. The relation of the number of memorybanks per flash memory chip and the write speed will now be describedfor each of the writing operation modes.

FIG. 6 shows the writing operation timings and write speed for each ofthe writing operation modes. In FIG. 6, the write unit of the writingoperation is N bytes. The write speed of a flash memory chip having onememory bank is expressed as N/(Tsetup+Tprog) [Bytes/sec].

The write speed in the case of performing simultaneous writing on Smemory banks in a flash memory chip having S memory banks is expressedas S·N/(S·Tsetup+Tprog) [Bytes/sec].

The write speed in the case of performing interleave writing on S memorybanks in the flash memory chip having S memory banks varies according tothe relation between (S−1)·Tsetup and Tprog. In other words, the writespeed varies according to whether the writing operation on the memorybank BNK1 has been already finished or not on completion of the setupoperation on the memory banks BNK1 to BNKS. When (S−1)·Tsetup≧Tprog, thewrite speed is expressed as N/Tsetup [Bytes/sec]. When(S−1)·Tsetup<Tprog, the write speed is expressed as S·N/(Tsetup+Tprog)[Bytes/sec].

FIG. 7 shows the relation between the number of memory banks per flashmemory in each of the interleave writing and simultaneous writing andthe write speed described with reference to FIG. 6 when N=2 Kbytes,Tsetup=100 μsec, and Tprog=1000 μsec. In the case of interleave writing,when the number of memory banks is increased to a certain value, even ifthe number is increased further, write operating speed is unchanged. Inthe case of simultaneous writing, as the number of banks increases, theincrease ratio of the writing operation speed gradually decreases. Whenthe number of banks is relatively small, the writing operation speed ofthe interleave writing and that of the simultaneous writing are almostthe same.

The relation between the number of memory banks in a plurality of flashmemory chips and the write speed will be described with respect to eachof the writing operation modes.

FIG. 8 shows writing operation timings and write operation speeds when Upieces of 1-bank flash memory chips are used. The operation mode isequivalent to the interleave writing operation mode on one flash memorychip having U memory banks and corresponds to the S-bank interleavewriting operation in FIG. 6. When (U−1)·Tsetup≧Tprog, the write speed isexpressed as N/Tsetup [Bytes/sec]. When (U−1)·Tsetup<Tprog, the writespeed is expressed as U·N/(Tsetup+Tprog) [Bytes/sec].

FIG. 9 shows simultaneous writing operation timings and write operationspeeds when U pieces of S-bank flash memory chips are used. Theoperation mode corresponds to a process of U times of the S-banksimultaneous writing operation in FIG. 6. The write speed variesaccording to the relation between S(U−1)·Tsetup and Tprog. Specifically,the write speed is determined according to whether the interleavewriting on all of memory banks BNK1 to BNKS in one chip CHP1 has beenalready finished or not on completion of the setup operation on thememory banks of all of the chips CHP1 to CHPU. When S(U−1)·Tsetup≧Tprog,the write speed is expressed as N/Tsetup [Bytes/sec]. WhenS(U−1)·Tsetup<Tprog, the write speed is expressed asS·U·N/(S·Tsetup+Tprog) [Bytes/sec].

FIG. 10 shows the interleave writing operation timings and writingoperation speeds when U pieces of S-bank flash memory chips are used.The operation mode is equivalent to the interleave writing operationmode on one flash memory chip having S·U memory banks and corresponds tothe process of U times of the S-bank interleave writing operation inFIG. 6. The write speed varies according to the relation between(S·U−1)·Tsetup and Tprog. Specifically, the write speed is determinedaccording to whether the interleave writing on one memory bank BNK1 inone chip CHP1 has been already finished or not on completion of thesetup operation on the memory banks of all of the chips CHP1 to CHPU.When (SU−1)·Tsetup≧Tprog, the write speed is expressed as N/Tsetup[Bytes/sec]. When (SU−1)·Tsetup<Tprog, the write speed is expressed asS·U·N/(Tsetup+Tprog) [Bytes/sec].

The case where the write speed becomes N/Tsetup [Bytes/sec] in thewriting operation modes of FIGS. 8 to 10, that is, a state where thewrite speed does not increase even if the number of chips is increaseddenotes a state where setup data and write data can be always sent fromthe memory controller 5 to the flash memory chips. The number of chipsat the boundary point at which the write speed does not increase even ifthe number of chips is increased gives the minimum value of the area ofthe system at which the write speed in each of the writing operationmodes becomes the maximum, in short, the minimum value of the number offlash memory chips. From this viewpoint, FIG. 11 shows the relationbetween the number of chips and the number of memory banks at which thewrite speed becomes the maximum in each of the writing operation modesof FIGS. 8 to 10. In the diagram, the conditions are: Tsetup=100 μsecand Tprog=1000 μsec. It is clarified from FIG. 11 that by performing thesimultaneous writing or interleave writing in the memory chip by usingthe flash memory chip having the multibank configuration having aplurality of memory banks which can operate independent of each other,the number of flash memory chips necessary to construct the memorysystem having high writing speed can be reduced.

As described above, in the selectable simultaneous writing operation,the writing operation which is much longer than the write setup time canbe performed perfectly in parallel on the multiple banks of the multiplechips. In the selectable interleave writing operation, the writingoperation following the write setup on one memory bank in the multiplebanks in the multiple chips is sequentially performed and partiallyoverlaps the writing operation on another memory bank, therebyperforming the operations in parallel. Thus, the number of nonvolatilememory chips constructing the memory system performing the high-speedwriting operation can be made relatively small.

The memory controller discriminates between the instruction of thesimultaneous writing operation and the instruction of the interleavewriting operation in accordance with the kind of the command code forinstructing the writing operation, accompanying the write addressinformation and the write data information. Alternately, the instructioncan be given by register setting. However, as compared with the registersetting, the method of the invention can omit a special control mode. Itis sufficient to supply a write command so as to accompany the writeaddress information and the write data information.

Application to Multimedia Card

FIG. 12 illustrates a multimedia card to which the invention is applied.A multimedia card 11 has card dimensions of 24 mm×32 mm×1.4 mm inspecifications according to a standardization group. A card board 12has, as connection terminals, a connection terminal 13 a for inputting acard select signal CS, a connection terminal 13 b for inputting acommand CMD, a connection terminal 13 c for inputting a clock signalCLK, a connection terminal 13 d for inputting/outputting data DAT, aconnection terminal 13 e to which the power source voltage Vcc issupplied, and two connection terminals 13 f and 13 g to which the groundvoltage Vss is supplied.

The card board 12 is provided with an interface driver 14, the memorycontroller 5, the SRAM 6, and the flash memory chips CHP1 and CHP2. Thememory controller 5 has an interface control unit 15 and a memorycontrol unit 16. The interface control unit 15 has a control logiccircuit for host interface control, file control, and data transfercontrol. The interface control unit 15 receives a command supplied froma host system via the interface driver 14, decodes the command, andgives an operation instruction to the memory control unit 16. The memorycontrol unit 16 receives the instruction and controls an access to filedata in the flash memory chips CHP1 and CHP2. For example, the interfacecontrol unit 15 temporarily stores write data supplied from the outsideinto the SRAM and instructs the memory control unit 16 to performsimultaneous writing on the multiple banks in the multiple chips orinterleave writing on the multiple banks in the multiple chips. Inaccordance with the instruction, the memory control unit 16 supplies thecommand code and write data to the flash memory chips CHP1 and CHP2 andcontrols the simultaneous writing on the multiple banks in the multiplechips or the interleave writing on the multiple banks of the multiplechips.

The write speeds in various writing operation modes in the multimediacard 11 will now be described. The characteristics of the flash memorychips CHP1 and CHP2 are set as Tsetup=100 μsec, Tprog=2000 μsec, and onesector as a write unit corresponding to N has 2 Kbytes. Since data isserially input in cycles of 50 nsec from the host system to the dataterminal DAT, it takes about 0.82 msec (≈2048×8×50) to input the writedata of 2 Kbytes to the data terminal DAT.

FIG. 13 illustrates writing operation timings of the operation modeusing only one memory bank of one flash memory chip (mode of using onebank in one chip). The data transfer speed from the host system to thememory card in this case is 0.67 Mbytes/sec.

FIG. 14 illustrates writing operation timings of the operation modeusing one memory bank of each of two flash memory chips (mode of usingone bank in each of two chips). The data transfer speed from the hostsystem to the memory card in this case is 1.34 Mbytes/sec.

FIG. 15 illustrates writing operation timings of the operation mode ofperforming simultaneous writing on two memory banks in one flash memorychip (mode of performing simultaneous writing on two banks in one chip)The data transfer speed from the host system to the memory card in thiscase is 1.04 Mbytes/sec.

FIG. 16 illustrates writing operation timings of the operation mode ofperforming simultaneous writing on two memory banks in each of two flashmemory chips (mode of performing simultaneous writing on two banks ineach of two chips). The data transfer speed from the host system to thememory card in this case is 2.08 Mbytes/sec.

FIG. 17 illustrates writing operation timings of the operation mode ofperforming interleave writing on two memory banks in one memory chip(mode of performing interleave writing on two banks in one chip). Thedata transfer speed from the host system to the memory card in this caseis 1.24 Mbytes/sec.

FIG. 18 illustrates writing operation timings of the operation mode ofperforming interleave writing on two memory banks in each of two flashmemory chips (mode of performing interleave writing on two banks in eachof two banks). The data transfer speed from the host system to thememory card in this case is 2.38 Mbytes/sec.

As understood from the results of operation speeds of the operationmodes in FIGS. 13 to 18, in the case of employing two operation modes ofthe operation mode of performing simultaneous writing on two banks ineach of two banks as shown in FIG. 16 and the operation mode ofperforming interleave writing on two banks in each of two chips, thedata transfer speed from the host system side can be made relativelyhigh. The operation mode of using the simultaneous writing on two banksin each of two chips shown in FIG. 16 is one mode of the simultaneouswriting on S banks in each of plural chips in FIG. 9. The operation modeof performing interleave writing on two banks in each of two chips shownin FIG. 18 is one mode of the S-bank interleave writing of FIG. 10. Itbecomes therefore more apparent that, by employing the simultaneouswriting operation or interleave writing operation on multiple banks inmultiple chips, a memory system of a high-speed writing process can beconstructed.

Either the simultaneous writing or interleave writing is employedarbitrarily on the host system side. In the case of FIG. 18, althoughthe processing speed in the case of FIG. 18 is the highest, the hostsystem has to continuously send the write command and write data withoutintermission. In the case of FIG. 16, a slightly busy state occurs onthe memory card side and the processing speed slightly decreases.However, the host system can have freedom of performing another processduring the period of the busy state.

General Configuration of Flash Memory

FIG. 19 shows an example of the flash memory chip CHP1 as a whole.

The flash memory chip CHP1 has, on one semiconductor board(semiconductor chip) 22 made of single crystal silicon or the like,plural memory banks, for example, two memory banks BNK1 and BNK2 whichcan operate independent of each other, a control unit 25 for controllingthe memory operation on the two memory banks BNK1 and BNK2, statusregisters 26 and 27 provided for the memory banks BNK1 and BNK2, aninterface control unit 28 as an interface to the outside, repaircircuits 29 and 30 assigned to the memory banks BNK1 and BNK2,respectively, an address buffer 31, an address counter 32, and aninternal power source circuit 33. The control unit 25 includes a commanddecoder 40, a processor (which will be also simply described as CPU) 41having a CPU (Central Processing Unit) and an operation program memory(PGM), and a data input/output control unit 42.

The input/output terminal I/O[7:0] of the flash memory chip CHP1 is usedcommonly for address input, data input/output, and command input. An Xaddress signal input from the input/output terminal I/O[7:0] is suppliedto the X address buffer 31 via the interface control unit 28, and aninput Y address signal is preset in the Y address counter 32 via theinterface control unit 28. A command input from the input/outputterminal I/0[7:0] is supplied to the command decoder 40 via theinterface control unit 28. Write data to be supplied from theinput/output terminal I/0[7:0] to the memory banks BNK1 and BNK2 issupplied to the data input/output control circuit 42 via the interfacecontrol unit 28. Read data from the memory banks BNK1 and BNK2 issupplied from the data input/output control circuit 42 to theinput/output terminal I/O[7:0] via the interface control unit 28. Asignal input/output to/from the input/output terminal I/O[7:0] is alsocalled a signal I/O[7:0] for convenience.

The interface control unit 28 inputs, as access control signals, thechip enable signal /CE, output enable signal /OE, write enable signal/WE, serial clock signal SC, reset signal /RES, and command enablesignal /CDE. The sign “/” attached at the head of the signal nameindicates that the signal is enable low. The interface control unit 28controls a signal interface function to the outside or the like inaccordance with the state of each of the signals.

Each of the memory banks BNK1 and BNK2 has a number of nonvolatilememory cells capable of rewriting stored information. A part of thenonvolatile memory cells is a repair (redundant) memory cell with whicha defective memory cell is replaced. Each of the repair circuits 29 and30 has a program circuit (not shown) capable of programming an addressof a defective memory cell to be replaced with the repair memory celland an address converter (not shown) for determining whether theprogrammed address to be repaired is designated as an access address ornot. An X address signal for selecting a nonvolatile memory cell fromthe memory banks BNK1 and BNK2 is output from the address buffer 31, anda Y address signal for selecting a nonvolatile memory cell from thememory banks BNK1 and BNK2 is output from the address counter 32. The Xaddress signal and the Y address signal are supplied to the repaircircuits 29 and 30. If the signal indicates an address of a nonvolatilememory cell to be repaired, the address is replaced. If the signal doesnot indicate an address of a nonvolatile memory cell to be repaired, thesignal is passed through and supplied to the memory banks BNK1 and BNK2.

Each of the memory banks BNK1 and BNK2 includes, although not limited,as shown in FIG. 20, a memory cell array 50, an X address decoder 51, aY address decoder 52, a Y switch circuit 53, a sense latch circuit 54,and a data latch circuit 55. The memory cell array 50 has a number ofelectrically erasable and programmable nonvolatile memory cells. Forexample, as shown in FIG. 21, a nonvolatile memory cell MC has a sourceS and a drain D formed in a semiconductor substrate or a memory wellSUB, a floating gate FG formed over a channel region via an oxide film,and a control gate CG overlapping the floating gate FG via an interlayerinsulating film. In the memory cell array 50, in the case of an AND-typearray illustrated in FIG. 22, a sub bit line SBL illustratedrepresentatively is connected to a main bit line MBL via a selection MOStransistor M1, and the drain of the nonvolatile memory cell MC iscoupled to the sub bit line SBL. The sources of nonvolatile memory cellsMC sharing the sub bit line SBL are commonly connected to a source lineSL via a second selection MOS transistor M2. Switching of the firstselection MOS transistor M1 is controlled by a bit line control line SDion a row direction unit basis and switching of the second selection MOStransistor M2 is controlled by a source line control line SSi on the rowdirection unit basis.

The X address decoder 51 in FIG. 20 decodes an X address signal, andselects the word line WL, bit line control line SDi, and source linecontrol line SSi in accordance with a designated memory operation. The Yaddress decoder 52 decodes the Y address signal output from the addresscounter 32, and generates a switching control signal of the Y switchcircuit 53 for bit line selection. The data latch circuit 55 has thefunction of a data buffer for temporarily holding write data input fromthe outside on the byte unit basis. The sense latch circuit 54 sensesand latches stored information read from a nonvolatile memory cell andholds write control data for writing operation given from the data latchcircuit 55.

Data in the memory cells is erased in a lump on a word line unit basis(which is a sector unit basis) as shown in FIG. 23. −17V is applied to aselected word line, 0V is applied to a not-selected word line, and 0V isapplied to the source line.

As shown in FIG. 23, to write data into the memory cell, 17V is appliedto a write selection word line, 0V is applied to a write selection bitline, and 6V is applied to a not-selected bit line. As the write highvoltage application time increases, the threshold voltage of a memorycell rises. Either 0V or 6V is applied to a bit line is determined bythe logic value of write control information to be latched by the senselatch circuit.

The reading operation on the memory cell is performed in such a mannerthat, although not limited, 3.2V is applied to a read selection wordline, the source line is connected to the ground voltage of the circuit,1.0V is applied to the bit line via the sense latch circuit, and storedinformation is read according to a change in the bit line potentialbased on the presence or absence of current flowing from the bit line tothe source line in accordance with the threshold voltage of the memorycell.

The bit line selected by the Y address decoder 52 is connected to thedata input/output control circuit 42. Connection between the datainput/output control circuit 42 and the input/output terminal I/O[7:0]is controlled by the interface control unit 28.

The internal power source circuit 33 in FIG. 19 generates variousoperation powers for writing, erasing, verifying, reading, and the likeand supplies them to the memory banks BNK1 and BNK2.

The command decoder 40 and the CPU 41 control the whole memory operationsuch as simultaneous writing on multiple banks using the multiple chipsand interleave writing on multiple banks using the multiple chips inaccordance with an access command (also simply called command) suppliedfrom the interface control unit 28.

The command includes, although not limited, one or plural command codesand address information and data information necessary to execute thecommands in a predetermined format. Data information such as write dataincluded in a command is supplied to the data input/output controlcircuit 42. The address information included in the command is suppliedto the address buffer 31 and, as necessary, to the address counter 32 asdescribed above. The memory banks BNK1 and BNK2 are mapped to differentmemory addresses, and an X address signal supplied to the address buffer31 is regarded as a sector address for designating one of sector regionsin units of, for example, 2048 bits. Particularly, information as a partof the X address signal, for example, the uppermost address bit Am isregarded as memory bank designation information for instructing a memorybank to be subjected to the memory operation and supplied to the commanddecoder 40. The command decoder 40 instructs the CPU 41 to use thememory bank designated by memory bank designation information as anobject of the memory operation. The Y address signal supplied to theaddress counter 32 designates the position on an 8-bit unit basis in the2048-bit data of a sector address designated by the X address signal. Inan initial state of the memory operation, the address counter 32 isreset to the initial value “0”. When the Y address signal is supplied,the value is used as a preset value of the address counter 32. The Yaddress counter 32 uses the initial value or preset value as a startaddress and sequentially outputs the Y address signal sequentiallyincremented as necessary to the memory banks BNK1 and BNK2.

The command decoder 40 in FIG. 19 decodes a command code included in acommand, determines a memory bank to operate by the memory bankdesignation information Am and supplies a result of decoding and aresult of determination to the CPU 41. On the basis of the results, theCPU 41 supplies access control signal CNT1 and CNT2 to the memory banksBNK1 and BNK2 to operate and controls the operations of the memory banksBNK1 and BNK2. When the memory operation is erasing or writing, a highvoltage is applied step by step, verifying operation is performed ineach step, and verification result information VFY1 and VFY2 is returnedto the CPU 41. When the verification result information VFY1 and VFY2indicates that a required threshold voltage state has not been reachedyet, if time is not up, the CPU 41 instructs application of a highvoltage at the next step by the access control signals CNT1 and CNT2.When the verification result information VFY1 and VFY2 indicates thatthe required threshold voltage state has not been achieved yet evenafter time is up, the CPU 41 gives a fail status to the status registers26 and 27 by fail/pass information FP1 and FP2. The command decoder 40outputs operation mode information MD1 and MD2 adapted to an operationinstructed by a command given at that time to the status registers 26and 27. The status registers 26 and 27 determine the cause of fail orpass notified by the fail/pass information FP1 and FP2 by the operationmode information MD1 and MD2 and sets a fail or pass state in acorresponding register bit. The command decoder 40 inputs statusinformation ST1 and ST2 held by the status registers 26 and 27 and, withreference to the information, determines whether a new input command canbe accepted or not. For example, if the memory bank BNK1 is in a writefail state, an access command designating the memory bank BNK1 can beaccepted only when the access command is a predetermined command such asa write retry command.

The status registers 26 and 27 hold information indicative of a statusof a memory operation for each of memory banks. The information held bythe two status registers 26 and 27 can be read from the input/outputterminal I/O[7:0] by asserting the output enable signal /OE.

FIG. 24 illustrates access commands of the flash memory chip CHP1. Theaccess commands are roughly divided into read operation commands A, anerase operation command B, write operation commands C, and statusregister resetting commands D. The diagram shows the command names,meaning, and basic command formats.

A first serial read command (Serial Read (1)) is a command for reading adata region in a sector. A second serial read command (Serial Read (2))is a command for reading a management region of a sector. An ID readcommand (Read Identifier Codes) is a command for reading a siliconsignature such as storage capacity or serial number of the flash memorychip. A first data recovery read command (Data Recovery Read (1))instructs to output write data held in a memory bank which enters awrite fail state in a writing operation on a memory bank to the outside.A second data recovery read command (Data Recovery Read (2)) instructsan operation of outputting write data held in the memory bank BNK1 whichenters a write fail state during a writing operation on two memory banksto the outside. A third data recovery read command (Data Recovery Read(3)) instructs an operation of outputting write data held in the memorybank BNK2 which enters a write fail state during a writing operation ontwo memory banks to the outside. The data recovery commands are used tooutput write data held in a flash memory to the outside when a writefail occurs so that a host apparatus can write data to another flashmemory.

The sector erase command (Sector Erase) instructs an erasing operationon a sector unit basis.

A first write command (Program(1)) instructs a writing operationincluding a sector erasing sequence. A second write command (Program(2))instructs a writing operation on the data region in a sector. A thirdwrite command (Program(3)) instructs a writing operation on themanagement region in a sector. A fourth write command (Program(4))instructs additional writing. The additional writing is a writingoperation on a storage region or the like as a part of the managementregion. A program retry command (“Program Retry” command) instructs toretry a writing operation on another sector in the same memory bank whenwrite fail occurs.

At the head of each of the various access commands, a command code suchas “00H” expressed in hexadecimal notation is disposed. A command suchas the ID read command (Read Identifier Codes) as a part of the commandsis constructed by only a command code. In an access command requiringaddress information, sector address information SA1 and SA2 is disposedsubsequent to the command code. The total number of bits of the sectoraddress information SA1 and SA2 is 16. One sector address (X addressinformation) is constructed by 16 bits. In case of reading or writing apart of a sector from some midpoint of the sector, it is sufficient toadd Y address information after the sector address information. In thecase where write data is necessary as in the writing operation, writedata follows the Y address information.

In a sector erase command, a command code “B0H” instructs start of theerasing operation. As a command for instructing erasing of a sector in amemory bank, it is sufficient to add the command code “B0H” after thesector address information SA1 and SA2 to be erased. In the case ofinstructing erasing of sectors in parallel in two memory banks, it issufficient to dispose second sector address information SA1

1 and SA2

1 subsequent to the first sector address information SA1 and SA2 andfinally add the command code “B0H”. Memory banks designated by thesecond sector address information SA1

1 and SA2

1 have to be different from memory banks designated by the first sectoraddress information SA1 and SA2. No separator code is necessary betweenthe first sector address information SA1 and SA2 and the second sectoraddress information SA1

1 and SA2

1 for the reason that Y address information and data information isunnecessary to erase a sector.

In the first to fourth write access commands and the program retrycommand, a command code “40H” is a command code for instructing start ofthe writing operation. In the case of writing two memory banks inparallel, a command code “41H” is interposed as a separator code betweeninstruction information such as addresses and write data to both of thememory banks BNK1 and BNK2. Since designation of a Y address (presetaddress into the address counter) is arbitrary in the writing operation,the separator code is necessary. The separator code “41H” may beregarded as a command code instructing parallel writing operation. Inthe writing operation, the memory banks designated by the second sectoraddress information SA1

1 and SA2

1 have to be different from memory banks designated by the first sectoraddress information SA1 and SA2. The 2-bank parallel write command isnot an object of the interleave operation. In the program retry command,sector addresses SA1

3 and SA2

3 have to select banks failed to be written. Whether the limitationarticles are fulfilled or not is determined by the command decoder 40.

The invention achieved by the inventors herein has been concretelydescribed above on the basis of the embodiment. Obviously, the inventionis not limited to the embodiment but can be variously modified withoutdeparting from the gist.

For example, the nonvolatile memory chip is not limited to a flashmemory cell but may be an MNOS, a high-dielectric memory cell, or thelike. Information stored in a memory cell is not limited to binary databut may be multivalue data such as four-value data. In the case of amemory cell capable of storing multivalue data, multivalue data isstored according to variations in the threshold voltages or by locallyaccumulating charges in a storage gate. The configuration of the memorycell array in the flash memory is not limited to the AND type but may beproperly changed to the NOR type, the NAND type, or the like. Thethreshold voltages for erasing and writing operations can be alsodefined different from those of the specification.

The kinds of commands, methods of designating a sector address, a methodof inputting write data, and the like may be different from the above.For example, the input terminals do not have to be dedicated to data,address and command. The number of memory banks is not limited to twobut may be three or more.

Obviously, the form of the memory card is not limited to a multimediacard but the invention can be also applied to memory cards according toother standards. An example of the memory cards is a memory card havinga plurality of terminals for inputting/outputting data and capable ofinputting/outputting data in parallel. The memory system is not limitedto a memory card. As a part of a data processing system constructed bymounting a microprocessor, a memory, and the like onto a circuit board,a flash memory chip and a control chip may be mounted.

Effects obtained by representative ones of the inventions disclosed inthe application will be briefly described as follows.

Since the simultaneous writing operation or the interleave writingoperation on a plurality of memory banks in a plurality of nonvolatilememory chips can be selected, in the simultaneous writing operation, thewriting operation much longer than setup time can be performed perfectlyin parallel. In the interleave writing operation, the writing operationfollowing the write setup can be performed so as to partially overlapthe writing operation on another memory bank. As a result, the number ofnonvolatile memory chips required to construct a memory systemperforming a high-speed writing process can be made relatively small. Inshort, the invention can provide a memory system and, further, a memorycard of which writing speed can be increased without mounting a largenumber of flash memory chips to an extent that the size and cost of thememory card increases.

INDUSTRIAL APPLICABILITY

The invention can be widely applied to a memory card of a predeterminedform such as a multimedia card, a processor board on which a flashmemory and a microprocessor are mounted, and the like.

1-29. (canceled)
 30. A nonvolatile memory apparatus comprising: a firstterminal used for inputting/outputting data; a second terminal used forinputting an operation instruction command; a third terminal used forinputting a clock instructing a timing of inputting/outputting data andinputting the operation instruction command; a control unit whichcontrols an operation according to the operation instruction commandinput from the second terminal; and at least one nonvolatile memory usedfor storing data received via the first terminal based on control of thecontrol unit, wherein said nonvolatile memory has a plurality of memorycells, each of belonging to a corresponding one of a plurality ofblocks, and is capable of performing a data storing operation for afirst block during performance of a data storing operation for a secondblock.
 31. A nonvolatile memory apparatus according to claim 30, whereinsaid nonvolatile memory has a plurality of signals for respectiveblocks, and wherein each signal is for indicating whether the datastoring operation is performing or not in an associated block.
 32. Anonvolatile memory apparatus according to claim 31, further comprising asecond nonvolatile memory, wherein the control unit issues a programcommand to a selected one of the nonvolatile memories, and is capable ofissuing the program command to the other nonvolatile memory duringperformance of the data storing operation in the selected nonvolatilememory.
 33. A nonvolatile memory apparatus comprising: a first terminalused for inputting/outputting data; a second terminal used for inputtingan operation instruction command; a third terminal used for inputting aclock instructing a timing of inputting/outputting data and inputtingthe operation instruction command; a control unit which controls anoperation according to the operation instruction command input from thesecond terminal; and at least one nonvolatile memory which performs aprogram operation for storing data received via the first terminal inaccordance with a program command issued from the control unit, whereinsaid nonvolatile memory has a plurality of memory cells, each belongingto a corresponding one of a plurality of blocks, and is capable ofreceiving the program command for storing data to a first block duringperformance the program operation for storing data to a second block.34. A nonvolatile memory apparatus according to claim 33, wherein saidnonvolatile memory has a plurality of signals for respective blocks, andwherein each signal is for indicating whether the program operation isperforming or not in an associated block.
 35. A nonvolatile memoryapparatus according to claim 34, further comprising a second nonvolatilememory, wherein the control unit operates to issue the program commandto the second nonvolatile memory during performance the programoperation in said one nonvolatile memory.
 36. A nonvolatile memoryapparatus according to claim 31, wherein the control unit operates toissue the program command to the second nonvolatile memory duringperformance the program operation in said one nonvolatile memory.